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SiFive /FE310 /QSPI0 /fmt

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Single)protocol 0 (Big)endian 0 (Rx)direction 0length

protocol=Single, endian=Big, direction=Rx

Description

Frame Format Register

Fields

protocol

0 (Single): DQ0 (MOSI), DQ1 (MISO)

1 (Dual): DQ0, DQ1

2 (Quad): DQ0, DQ1, DQ2, DQ3
endian

0 (Big): Transmit MSB first.

1 (Little): Transmit LSB first.
direction

0 (Rx): For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal.

1 (Tx): The receive FIFO is not populated.
length

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data