DDR PLL Configuration Register
| divr | PLL reference divider value minus one |
| divf | PLL feedback divider value minus one |
| divq | Log2 of PLL output divider. Valid settings are 1,2,3,4,5,6 |
| range | PLL filter range. 3’b100 = 33MHz |
| bypass | PLL bypass |
| fse | Internal or external input path. Valid settings is 1, internal feedback. |
| lock | PLL locked |