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SiFive /FU540 /PRCI /ddrpllcfg1

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Interpret as ddrpllcfg1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (cke)cke

Description

DDR PLL Configuration Register

Fields

cke

PLL clock output enable. Glitch free clock gate after PLL output. 1 enables clock, 0 disables clock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data