Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/SiFive/sifive_hifive_unmatched_a00/riscv_plic0_0/enable_0_0#0x0
ENABLE Register for interrupt ids 31 to 0 for hart 0
https://github.com/cmsis-svd/cmsis-svd-data