Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/SiFive/sifive_hifive_unmatched_a00/riscv_plic0_0/enable_1_2#0x0
ENABLE Register for interrupt ids 63 to 32 for hart 2
https://github.com/cmsis-svd/cmsis-svd-data