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SiFive /sifive_hifive_unmatched_a00 /sifive_i2c0_1 /command__status

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Interpret as command__status

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (wr_iack__rd_if)wr_iack__rd_if 0 (wr_res__rd_tip)wr_res__rd_tip 0 (wr_res__rd_res)wr_res__rd_res 0 (wr_ack__rd_res)wr_ack__rd_res 0 (wr_txd__rd_res)wr_txd__rd_res 0 (wr_rxd__rd_al)wr_rxd__rd_al 0 (wr_sto__rd_busy)wr_sto__rd_busy 0 (wr_sta__rd_rxack)wr_sta__rd_rxack

Description

Command write and status read register

Fields

wr_iack__rd_if

Clear interrupt and Interrupt pending
wr_res__rd_tip

Reserved and Transfer in progress
wr_res__rd_res

Reserved and Reserved
wr_ack__rd_res

Send ACK/NACK and Reserved
wr_txd__rd_res

Transmit data and Reserved
wr_rxd__rd_al

Receive data and Arbitration lost
wr_sto__rd_busy

Generate stop and I2C bus busy
wr_sta__rd_rxack

Generate start and Got ACK/NACK

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data