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SiFive /sifive_hifive_unmatched_a00 /sifive_spi0_1 /sampledel

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Interpret as sampledel

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0sd

Description

Number of delay stages from slave to the SPI controller

Fields

sd

Number of delay stages from slave to SPI controller

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data