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SiFive /sifive_hifive_unmatched_a00 /sifive_spi0_2 /sckmode

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Interpret as sckmode

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (pha)pha 0 (pol)pol

Description

Serial clock mode

Fields

pha

Serial clock phase
pol

Serial clock polarity

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data