Regviz

Spansion /MB9BF36xx /RTC /WTTR0

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Interpret as WTTR0

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https://regviz.com/r/Spansion/MB9BF36xx/RTC/WTTR0#0x0

7 43 0 0 00 0 0 0 0 0 0 0 0 (TM0)TM0 0 (TM1)TM1 0 (TM2)TM2 0 (TM3)TM3 0 (TM4)TM4 0 (TM5)TM5 0 (TM6)TM6 0 (TM7)TM7

Description

register WTTR0

Fields

TM0

bitfield TM0
TM1

bitfield TM1
TM2

bitfield TM2
TM3

bitfield TM3
TM4

bitfield TM4
TM5

bitfield TM5
TM6

bitfield TM6
TM7

bitfield TM7

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data