Regviz

Toshiba /M061 /DSAD0 /CLK

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Interpret as CLK

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https://regviz.com/r/Toshiba/M061/DSAD0/CLK#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADCLK

Description

DSAD Conversion Clock Setting Register

Fields

ADCLK

ADCLK

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data