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stm32 /stm32c0 /STM32C011 /DMA /DMA_IFCR

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Interpret as DMA_IFCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CGIF1)CGIF1 0 (CTCIF1)CTCIF1 0 (CHTIF1)CHTIF1 0 (CTEIF1)CTEIF1 0 (CGIF2)CGIF2 0 (CTCIF2)CTCIF2 0 (CHTIF2)CHTIF2 0 (CTEIF2)CTEIF2 0 (CGIF3)CGIF3 0 (CTCIF3)CTCIF3 0 (CHTIF3)CHTIF3 0 (CTEIF3)CTEIF3

Description

DMA interrupt flag clear register

Fields

CGIF1

global interrupt flag clear for channel 1
CTCIF1

transfer complete flag clear for channel 1
CHTIF1

half transfer flag clear for channel 1
CTEIF1

transfer error flag clear for channel 1
CGIF2

global interrupt flag clear for channel 2
CTCIF2

transfer complete flag clear for channel 2
CHTIF2

half transfer flag clear for channel 2
CTEIF2

transfer error flag clear for channel 2
CGIF3

global interrupt flag clear for channel 3
CTCIF3

transfer complete flag clear for channel 3
CHTIF3

half transfer flag clear for channel 3
CTEIF3

transfer error flag clear for channel 3

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32