NBOOT0=B_0x0, BORR_LEV=B_0x0, SECURE_MUXING_EN=B_0x0, NBOOT_SEL=B_0x0, BOR_EN=B_0x0, HSE_NOT_REMAPPED=B_0x0, IRHEN=B_0x0, RAM_PARITY_CHECK=B_0x0, WWDG_SW=B_0x0, BORF_LEV=B_0x0, IWDG_STOP=B_0x0
FLASH option register
| RDP | Read protection level Other: Level 1, memories read protection active 170 (B_0xAA): Level 0, read protection not active 204 (B_0xCC): Level 2, chip read protection active |
| BOR_EN | Brown out reset enable 0 (B_0x0): Configurable brown out reset disabled, power-on reset defined by POR/PDR levels 1 (B_0x1): Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account |
| BORR_LEV | BOR threshold at falling VDD supply Falling VDD crossings this threshold activates the reset signal. 0 (B_0x0): BOR rising level 1 with threshold around 2.1 V 1 (B_0x1): BOR rising level 2 with threshold around 2.3 V 2 (B_0x2): BOR rising level 3 with threshold around 2.6 V 3 (B_0x3): BOR rising level 4 with threshold around 2.9 V |
| BORF_LEV | BOR threshold at falling VDD supply Falling VDD crossings this threshold activates the reset signal. 0 (B_0x0): BOR falling level 1 with threshold around 2.0 V 1 (B_0x1): BOR falling level 2 with threshold around 2.2 V 2 (B_0x2): BOR falling level 3 with threshold around 2.5 V 3 (B_0x3): BOR falling level 4 with threshold around 2.8 V |
| NRST_STOP | None |
| NRST_STDBY | None |
| NRST_SHDW | None |
| IWDG_SW | None |
| IWDG_STOP | Independent watchdog counter freeze in Stop mode 0 (B_0x0): Independent watchdog counter is frozen in Stop mode 1 (B_0x1): Independent watchdog counter is running in Stop mode |
| IWGD_STDBY | None |
| WWDG_SW | Window watchdog selection 0 (B_0x0): Hardware window watchdog 1 (B_0x1): Software window watchdog |
| HSE_NOT_REMAPPED | HSE remapping enable/disable When cleared, the bit remaps the HSE clock source from PF0-OSC_IN/PF1-OSC_OUT pins to PC14-OSCX_IN/PC15-OSCX_OUT. Thus PC14-OSCX_IN/PC15-OSCX_OUT are shared by both LSE and HSE and the two clock sources cannot be use simultaneously. On packages with less than 48 pins, the remapping is always enabled (PF0-OSC_IN/PF1-OSC_OUT are not available), regardless of this bit. As all STM32C011xx packages have less than 48 pins, this bit is only applicable to STM32C031xx. Note: On 48 pins packages, when HSE_NOT_REMAPPED is reset, HSE cannot be used in bypass mode. Refer to product errata sheet for more details. 0 (B_0x0): Enable 1 (B_0x1): Disable |
| RAM_PARITY_CHECK | SRAM parity check control enable/disable 0 (B_0x0): Enable 1 (B_0x1): Disable |
| SECURE_MUXING_EN | Multiple-bonding security The bit allows enabling automatic I/O configuration to prevent conflicts on I/Os connected (bonded) onto the same pin. If the software sets one of the I/Os connected to the same pin as active by configuring the SYSCFG_CFGR3 register, enabling this bit automatically forces the other I/Os in digital input mode, regardless of their software configuration. When the bit is disabled, the SYSCFG_CFGR3 register setting is ignored, all GPIOs linked to a given pin are active and can be set in the mode specified by the corresponding GPIOx_MODER register. The user software must ensure that there is no conflict between GPIOs. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| NBOOT_SEL | BOOT0 signal source selection This option bit defines the source of the BOOT0 signal. 0 (B_0x0): BOOT0 pin (legacy mode) 1 (B_0x1): nBOOT0 option bit |
| NBOOT1 | Boot configuration Together with the BOOT0 pin or option bit nBOOT0 (depending on nBOOT_SEL option bit configuration), this bit selects boot mode from the Main flash memory, SRAM or the System memory. Refer to Section 3: Boot configuration. |
| NBOOT0 | nBOOT0 option bit 0 (B_0x0): nBOOT0 = 0 1 (B_0x1): nBOOT0 = 1 |
| NRST_MODE | NRST pin configuration 1 (B_0x1): Reset input only: a low level on the NRST pin generates system reset; internal RESET is not propagated to the NRST pin. 2 (B_0x2): Standard GPIO: only internal RESET is possible 3 (B_0x3): Bidirectional reset: the NRST pin is configured in reset input/output (legacy) mode |
| IRHEN | Internal reset holder enable bit 0 (B_0x0): Internal resets are propagated as simple pulse on NRST pin 1 (B_0x1): Internal resets drives NRST pin low until it is seen as low level |