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stm32 /stm32c0 /STM32C011 /GPIOC /GPIOC_AFRL

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Interpret as GPIOC_AFRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0AFSEL00AFSEL10AFSEL20AFSEL30AFSEL40AFSEL50AFSEL60AFSEL7

Description

GPIO alternate function low register

Fields

AFSEL0

Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
AFSEL1

Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
AFSEL2

Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
AFSEL3

Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
AFSEL4

Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
AFSEL5

Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
AFSEL6

Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
AFSEL7

Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32