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stm32 /stm32c0 /STM32C011 /PWR /PWR_CR1

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Interpret as PWR_CR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LPMS0 (B_0x0)FPD_STOP 0 (B_0x0)FPD_SLP

FPD_STOP=B_0x0, LPMS=B_0x0, FPD_SLP=B_0x0

Description

PWR control register 1

Fields

LPMS

Low-power mode selection These bits select the low-power mode entered when CPU enters deepsleep mode. 1XX: Shutdown mode

0 (B_0x0): Stop mode

3 (B_0x3): Standby mode
FPD_STOP

Flash memory powered down during Stop mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode.

0 (B_0x0): Flash memory idle

1 (B_0x1): Flash memory powered down
FPD_SLP

Flash memory powered down during Sleep mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Sleep mode.

0 (B_0x0): Flash memory idle

1 (B_0x1): Flash memory powered down

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32