stm32 /stm32c0 /STM32C011 /RCC /RCC_CIFR

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Interpret as RCC_CIFR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LSIRDYF 0 (B_0x0)LSERDYF 0 (B_0x0)HSIRDYF 0 (B_0x0)HSERDYF 0 (B_0x0)CSSF 0 (B_0x0)LSECSSF

HSIRDYF=B_0x0, CSSF=B_0x0, LSECSSF=B_0x0, LSERDYF=B_0x0, LSIRDYF=B_0x0, HSERDYF=B_0x0

Description

RCC clock interrupt flag register

Fields

LSIRDYF

LSI ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit.

0 (B_0x0): Interrupt not pending

1 (B_0x1): Interrupt pending

LSERDYF

LSE ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit.

0 (B_0x0): Interrupt not pending

1 (B_0x1): Interrupt pending

HSIRDYF

HSI16 ready interrupt flag This flag indicates a pending interrupt upon HSI16 clock getting ready. Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit.

0 (B_0x0): Interrupt not pending

1 (B_0x1): Interrupt pending

HSERDYF

HSE ready interrupt flag This flag indicates a pending interrupt upon HSE clock getting ready. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit.

0 (B_0x0): Iterrupt not pending

1 (B_0x1): Interrupt pending

CSSF

HSE clock security system interrupt flag This flag indicates a pending interrupt upon HSE clock failure. Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit.

0 (B_0x0): Interrupt not pending

1 (B_0x1): Interrupt pending

LSECSSF

LSE clock security system interrupt flag This flag indicates a pending interrupt upon LSE clock failure. Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit.

0 (B_0x0): Interrupt not pending

1 (B_0x1): Interrupt pending

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