CSSON=B_0x0, HSERDY=B_0x0, HSIKERON=B_0x0, HSEBYP=B_0x0, HSION=B_0x0, HSEON=B_0x0, HSIKERDIV=B_0x0, SYSDIV=B_0x0, HSIDIV=B_0x0, HSIRDY=B_0x0
RCC clock control register
| SYSDIV | System clock division factor This bitfield controlled by software sets the division factor of the system clock divider to produce SYSCLK clock: 0 (B_0x0): 1 1 (B_0x1): 2 2 (B_0x2): 3 (reset value) 3 (B_0x3): 4 4 (B_0x4): 5 5 (B_0x5): 6 6 (B_0x6): 7 7 (B_0x7): 8 |
| HSIKERDIV | HSI48 kernel clock division factor This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock: 0 (B_0x0): 1 1 (B_0x1): 2 2 (B_0x2): 3 (reset value) 3 (B_0x3): 4 4 (B_0x4): 5 5 (B_0x5): 6 6 (B_0x6): 7 7 (B_0x7): 8 |
| HSION | HSI48 clock enable Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked with a clock derived from HSI48. This includes the exit from low-power modes and the system clock fall-back to HSI48 upon failing HSE oscillator clock selected as system clock source. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| HSIKERON | HSI48 always-enable for peripheral kernels. Set and cleared by software. Setting the bit activates the HSI48 oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI48 clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI48 as kernel clock. Note: Keeping the HSI48 active in Stop mode allows speeding up the serial interface communication as the HSI48 clock is ready immediately upon exiting Stop mode. 0 (B_0x0): HSI48 oscillator enable depends on the HSION bit 1 (B_0x1): HSI48 oscillator is active in Run and Stop modes |
| HSIRDY | HSI48 clock ready flag Set by hardware when the HSI48 oscillator is enabled through HSION and ready to use (stable). Note: Upon clearing HSION, HSIRDY goes low after six HSI48 clock cycles. 0 (B_0x0): Not ready 1 (B_0x1): Ready |
| HSIDIV | HSI48 clock division factor This bitfield controlled by software sets the division factor of the HSI48 clock divider to produce HSISYS clock: 0 (B_0x0): 1 1 (B_0x1): 2 2 (B_0x2): 4 (reset value) 3 (B_0x3): 8 4 (B_0x4): 16 5 (B_0x5): 32 6 (B_0x6): 64 7 (B_0x7): 128 |
| HSEON | HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| HSERDY | HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable and ready for use. Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles. 0 (B_0x0): Not ready 1 (B_0x1): Ready |
| HSEBYP | HSE crystal oscillator bypass Set and cleared by software. When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled. 0 (B_0x0): No bypass 1 (B_0x1): Bypass |
| CSSON | Clock security system enable Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset. 0 (B_0x0): Disable 1 (B_0x1): Enable |