IM7=B_0x0, IM23=B_0x0, IM9=B_0x0, IM1=B_0x0, IM8=B_0x0, IM25=B_0x0, IM15=B_0x0, IM6=B_0x0, IM19=B_0x0, IM11=B_0x0, IM10=B_0x0, IM4=B_0x0, IM13=B_0x0, IM5=B_0x0, IM12=B_0x0, IM3=B_0x0, IM0=B_0x0, IM14=B_0x0, IM2=B_0x0, IM31=B_0x0
EXTI CPU wakeup with interrupt mask register 1
| IM0 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM1 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM2 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM3 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM4 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM5 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM6 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM7 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM8 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM9 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM10 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM11 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM12 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM13 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM14 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM15 | CPU wakeup with interrupt mask on line x (x = 15 to 0) Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM19 | CPU wakeup with interrupt mask on line 19 Setting/clearing this bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM23 | CPU wakeup with interrupt mask on line 23 Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM25 | CPU wakeup with interrupt mask on line 25 Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |
| IM31 | CPU wakeup with interrupt mask on line 31 Setting/clearing this bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. 0 (B_0x0): wakeup with interrupt masked 1 (B_0x1): wakeup with interrupt unmasked |