SMBDEN=B_0x0, SBC=B_0x0, ERRIE=B_0x0, GCEN=B_0x0, ANFOFF=B_0x0, TXDMAEN=B_0x0, SMBHEN=B_0x0, STOPIE=B_0x0, ADDRIE=B_0x0, RXIE=B_0x0, PE=B_0x0, RXDMAEN=B_0x0, ALERTEN=B_0x0, NOSTRETCH=B_0x0, DNF=B_0x0, PECEN=B_0x0, TXIE=B_0x0, NACKIE=B_0x0, TCIE=B_0x0, WUPEN=B_0x0
I2C control register 1
| PE | Peripheral enable Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least three APB clock cycles. 0 (B_0x0): Peripheral disabled 1 (B_0x1): Peripheral enabled |
| TXIE | TX interrupt enable 0 (B_0x0): Transmit (TXIS) interrupt disabled 1 (B_0x1): Transmit (TXIS) interrupt enabled |
| RXIE | RX interrupt enable 0 (B_0x0): Receive (RXNE) interrupt disabled 1 (B_0x1): Receive (RXNE) interrupt enabled |
| ADDRIE | Address match interrupt enable (slave only) 0 (B_0x0): Address match (ADDR) interrupts disabled 1 (B_0x1): Address match (ADDR) interrupts enabled |
| NACKIE | Not acknowledge received interrupt enable 0 (B_0x0): Not acknowledge (NACKF) received interrupts disabled 1 (B_0x1): Not acknowledge (NACKF) received interrupts enabled |
| STOPIE | Stop detection interrupt enable 0 (B_0x0): Stop detection (STOPF) interrupt disabled 1 (B_0x1): Stop detection (STOPF) interrupt enabled |
| TCIE | Transfer complete interrupt enable Note: Any of these events generates an interrupt: Note: Transfer complete (TC) Note: Transfer complete reload (TCR) 0 (B_0x0): Transfer complete interrupt disabled 1 (B_0x1): Transfer complete interrupt enabled |
| ERRIE | Error interrupts enable Note: Any of these errors generates an interrupt: Note: Arbitration loss (ARLO) Note: Bus error detection (BERR) Note: Overrun/underrun (OVR) Note: Timeout detection (TIMEOUT) Note: PEC error detection (PECERR) Note: Alert pin event detection (ALERT) 0 (B_0x0): Error detection interrupts disabled 1 (B_0x1): Error detection interrupts enabled |
| DNF | Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK … Note: If the analog filter is enabled, the digital filter is added to it. This filter can be programmed only when the I2C is disabled (PE = 0). 0 (B_0x0): Digital filter disabled 1 (B_0x1): Digital filter enabled and filtering capability up to one tI2CCLK 15 (B_0xF): digital filter enabled and filtering capability up to fifteen tI2CCLK |
| ANFOFF | Analog noise filter OFF Note: This bit can be programmed only when the I2C is disabled (PE = 0). 0 (B_0x0): Analog noise filter enabled 1 (B_0x1): Analog noise filter disabled |
| TXDMAEN | DMA transmission requests enable 0 (B_0x0): DMA mode disabled for transmission 1 (B_0x1): DMA mode enabled for transmission |
| RXDMAEN | DMA reception requests enable 0 (B_0x0): DMA mode disabled for reception 1 (B_0x1): DMA mode enabled for reception |
| SBC | Slave byte control This bit is used to enable hardware byte control in slave mode. 0 (B_0x0): Slave byte control disabled 1 (B_0x1): Slave byte control enabled |
| NOSTRETCH | Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can be programmed only when the I2C is disabled (PE = 0). 0 (B_0x0): Clock stretching enabled 1 (B_0x1): Clock stretching disabled |
| WUPEN | Wake-up from Stop mode enable Note: If the wake-up from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. Note: WUPEN can be set only when DNF = 0000. 0 (B_0x0): Wake-up from Stop mode disabled. 1 (B_0x1): Wake-up from Stop mode enabled. |
| GCEN | General call enable 0 (B_0x0): General call disabled. Address 0b00000000 is NACKed. 1 (B_0x1): General call enabled. Address 0b00000000 is ACKed. |
| SMBHEN | SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. 0 (B_0x0): Host address disabled. Address 0b0001000x is NACKed. 1 (B_0x1): Host address enabled. Address 0b0001000x is ACKed. |
| SMBDEN | SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. 0 (B_0x0): Device default address disabled. Address 0b1100001x is NACKed. 1 (B_0x1): Device default address enabled. Address 0b1100001x is ACKed. |
| ALERTEN | SMBus alert enable Note: When ALERTEN = 0, the SMBA pin can be used as a standard GPIO. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. 0 (B_0x0): The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN = 1). In device mode (SMBHEN = 0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK). 1 (B_0x1): The SMBus alert pin is supported in host mode (SMBHEN = 1). In device mode (SMBHEN = 0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK). |
| PECEN | PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. 0 (B_0x0): PEC calculation disabled 1 (B_0x1): PEC calculation enabled |