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stm32 /stm32c0 /STM32C071 /PWR /PWR_CR2

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Interpret as PWR_CR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PVM_VDDIO2

PVM_VDDIO2=B_0x0

Description

PWR control register 1

Fields

PVM_VDDIO2

supply voltage monitoring

0 (B_0x0): Monitoring disabled; IOs in isolation mode

1 (B_0x1): Monitoring enabled; IOs enabled or in isolation mode according to VDDIO2 level

2 (B_0x2): Monitoring bypassed; IOs enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32