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stm32 /stm32c0 /STM32C071 /PWR /PWR_SR2

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Interpret as PWR_SR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)FLASH_RDY 0 (B_0x0)PVM_VDDIO2_OUT

PVM_VDDIO2_OUT=B_0x0, FLASH_RDY=B_0x0

Description

PWR status register 2

Fields

FLASH_RDY

Flash ready flag This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_SLP or FPD_STP bit. Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory.

0 (B_0x0): Flash memory in power-down

1 (B_0x1): Flash memory ready to be accessed
PVM_VDDIO2_OUT

VDDIO2 supply voltage monitoring output flag This flag indicates the readiness of the VDDIO2 supply voltage (excess of 1.2 V). The flag is cleared when the PVM of VDDIO2 is disabled (PVM_VDDIO2[0] = 0). Note: Only applicable on STM32C071xx, reserved on the other products.

0 (B_0x0): Not ready

1 (B_0x1): Ready

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32