SPI2EN=B_0x0, USBEN=B_0x0, RTCAPBEN=B_0x0, TIM3EN=B_0x0, PWREN=B_0x0, I2C1EN=B_0x0, I2C2EN=B_0x0, WWDGEN=B_0x0, TIM2EN=B_0x0, CRSEN=B_0x0, DBGEN=B_0x0, USART2EN=B_0x0
RCC APB peripheral clock enable register 1
| TIM2EN | TIM2 timer clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| TIM3EN | TIM3 timer clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| RTCAPBEN | RTC APB clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| WWDGEN | WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| USBEN | USB clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| SPI2EN | SPI2 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| CRSEN | CRS clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| USART2EN | USART2 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C1EN | I2C1 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C2EN | I2C2 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| DBGEN | Debug support clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| PWREN | Power interface clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |