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stm32 /stm32c0 /STM32C071 /RCC /RCC_APBSMENR1

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Interpret as RCC_APBSMENR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM2SMEN 0 (B_0x0)TIM3SMEN 0 (B_0x0)RTCAPBSMEN 0 (B_0x0)WWDGSMEN 0 (B_0x0)USBSMEN 0 (B_0x0)SPI2SMEN 0 (B_0x0)CRSSMEN 0 (B_0x0)USART2SMEN 0 (B_0x0)I2C1SMEN 0 (B_0x0)I2C2SMEN 0 (B_0x0)DBGSMEN 0 (B_0x0)PWRSMEN

I2C1SMEN=B_0x0, SPI2SMEN=B_0x0, TIM2SMEN=B_0x0, DBGSMEN=B_0x0, I2C2SMEN=B_0x0, USBSMEN=B_0x0, WWDGSMEN=B_0x0, RTCAPBSMEN=B_0x0, TIM3SMEN=B_0x0, PWRSMEN=B_0x0, USART2SMEN=B_0x0, CRSSMEN=B_0x0

Description

RCC APB peripheral clock enable in Sleep/Stop mode register 1

Fields

TIM2SMEN

TIM2 timer clock enable during Sleep mode Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices.

0 (B_0x0): Disable

1 (B_0x1): Enable
TIM3SMEN

TIM3 timer clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
RTCAPBSMEN

RTC APB clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
WWDGSMEN

WWDG clock enable during Sleep and Stop modes Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
USBSMEN

USB clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices.

0 (B_0x0): Disable

1 (B_0x1): Enable
SPI2SMEN

SPI2 clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices.

0 (B_0x0): Disable

1 (B_0x1): Enable
CRSSMEN

CRS clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices.

0 (B_0x0): Disable

1 (B_0x1): Enable
USART2SMEN

USART2 clock enable during Sleep and Stop modes Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
I2C1SMEN

I2C1 clock enable during Sleep and Stop modes Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
I2C2SMEN

I2C2 clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices.

0 (B_0x0): Disable

1 (B_0x1): Enable
DBGSMEN

Debug support clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
PWRSMEN

Power interface clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32