MCOSEL=B_0x0, SWS=B_0x0, SW=B_0x0, MCO2PRE=B_0x0, MCOPRE=B_0x0, MCO2SEL=B_0x0
RCC clock configuration register
| SW | System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected. 0 (B_0x0): HSISYS 1 (B_0x1): HSE 3 (B_0x3): LSI 4 (B_0x4): LSE |
| SWS | System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved 0 (B_0x0): HSISYS 1 (B_0x1): HSE 3 (B_0x3): LSI 4 (B_0x4): LSE |
| HPRE | AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 8 (B_0x8): 2 9 (B_0x9): 4 10 (B_0xA): 8 11 (B_0xB): 16 12 (B_0xC): 64 13 (B_0xD): 128 14 (B_0xE): 256 15 (B_0xF): 512 |
| PPRE | APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1 4 (B_0x4): 2 5 (B_0x5): 4 6 (B_0x6): 8 7 (B_0x7): 16 |
| MCO2SEL | Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: Other: reserved, must not be used Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching. On STM32C011xx and STM32C031xx, MCOSEL[3] is reserved. 0 (B_0x0): no clock 1 (B_0x1): SYSCLK 3 (B_0x3): HSI48 4 (B_0x4): HSE 6 (B_0x6): LSI 7 (B_0x7): LSE 8 (B_0x8): HSIUSB48 |
| MCO2PRE | Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: … Other: Reserved It is highly recommended to set this field before the MCO2 output is enabled. Note: Values above 0111 are only significant for STM32C071xx. On STM32C011xx and STM32C031xx devices, MCOPRE[3] is reserved. 0 (B_0x0): 1 1 (B_0x1): 2 2 (B_0x2): 4 7 (B_0x7): 128 8 (B_0x8): 256 9 (B_0x9): 512 10 (B_0xA): 1024 |
| MCOSEL | Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Other: reserved, must not be used Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. On STM32C011xx and STM32C031xx, MCOSEL[3] is reserved. 0 (B_0x0): no clock 1 (B_0x1): SYSCLK 3 (B_0x3): HSI48 4 (B_0x4): HSE 6 (B_0x6): LSI 7 (B_0x7): LSE 8 (B_0x8): HSIUSB48 |
| MCOPRE | Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: … Other: Reserved It is highly recommended to set this field before the MCO output is enabled. Note: Values above 0111 are only significant for STM32C071xx. On STM32C011xx and STM32C031xx devices, MCOPRE[3] is reserved. 0 (B_0x0): 1 1 (B_0x1): 2 2 (B_0x2): 4 7 (B_0x7): 128 8 (B_0x8): 256 9 (B_0x9): 512 10 (B_0xA): 1024 |