I2C2_FMP=B_0x0, I2C1_FMP=B_0x0, PA12_RMP=B_0x0, I2C_PA9_FMP=B_0x0, PA11_RMP=B_0x0, I2C_PB7_FMP=B_0x0, I2C_PB6_FMP=B_0x0, I2C_PA10_FMP=B_0x0, IR_POL=B_0x0, I2C_PC14_FMP=B_0x0, I2C_PB8_FMP=B_0x0, IR_MOD=B_0x0, I2C_PB9_FMP=B_0x0
SYSCFG configuration register 1
| MEM_MODE | Memory mapping selection bits This bitfield controlled by software selects the memory internally mapped at the address 0x0000 0000. Its reset value is determined by the boot mode configuration. Refer to Section 3: Boot configuration for more details. x0: Main Flash memory 1 (B_0x1): System Flash memory 3 (B_0x3): Embedded SRAM |
| PA11_RMP | PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. Note: If the PINMUX2[1:0] bitfield of the SYSCFG_CFGR3 register is at 00, PA11_RMP must be kept at 0 to prevent conflict due to two GPIO outputs with different output levels connected to the same pin. 0 (B_0x0): No remap (PA11) 1 (B_0x1): Remap (PA9) |
| PA12_RMP | PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. Note: If the PINMUX4[1:0] bitfield of the SYSCFG_CFGR3 register is at 00, PA12_RMP must be kept at 0 to prevent conflict due to two GPIO outputs with different output levels connected to the same pin. 0 (B_0x0): No remap (PA12) 1 (B_0x1): Remap (PA10) |
| IR_POL | IR output polarity selection 0 (B_0x0): Output of IRTIM (IR_OUT) is not inverted 1 (B_0x1): Output of IRTIM (IR_OUT) is inverted |
| IR_MOD | IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope: 0 (B_0x0): TIM16 1 (B_0x1): USART1 2 (B_0x2): USART2 |
| I2C_PB6_FMP | Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port. 0 (B_0x0): Disable disabled if not enabled through I2Cx_FMP 1 (B_0x1): Enable |
| I2C_PB7_FMP | Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port. 0 (B_0x0): Disable disabled if not enabled through I2Cx_FMP 1 (B_0x1): Enable |
| I2C_PB8_FMP | Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port. Note: Not available on STM32C011xx. 0 (B_0x0): Disable disabled if not enabled through I2Cx_FMP 1 (B_0x1): Enable |
| I2C_PB9_FMP | Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port. Note: Not available on STM32C011xx. 0 (B_0x0): Disable disabled if not enabled through I2Cx_FMP 1 (B_0x1): Enable |
| I2C1_FMP | Fast Mode Plus (FM+) enable for I2C1 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers. 0 (B_0x0): Disable disabled if not enabled through I2C_y_FMP 1 (B_0x1): Enable |
| I2C2_FMP | Fast Mode Plus (FM+) enable for I2C2 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C2 through GPIOx_AFR registers. Note: Only applicable to STM32C071xx. Reserved on the other products. 0 (B_0x0): Disable disabled if not enabled through I2C_y_FMP 1 (B_0x1): Enable |
| I2C_PA9_FMP | Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port. 0 (B_0x0): Disable disabled if not enabled through I2Cx_FMP 1 (B_0x1): Enable |
| I2C_PA10_FMP | Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port. 0 (B_0x0): Disable disabled if not enabled through I2Cx_FMP 1 (B_0x1): Enable |
| I2C_PC14_FMP | Fast Mode Plus (FM+) enable for PC14 This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port. Note: Not available on STM32C011xx. 0 (B_0x0): Disable if not enabled through I2Cx_FMP 1 (B_0x1): Enable |