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stm32 /stm32c0 /STM32C071 /SYSCFG /SYSCFG_CFGR3

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Interpret as SYSCFG_CFGR3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1)PINMUX0 0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4)PINMUX1 0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5)PINMUX2 0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8)PINMUX3 0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2)PINMUX4 0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1)PINMUX5

PINMUX2=B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5, PINMUX3=B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8, PINMUX5=B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1, PINMUX1=B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4, PINMUX0=B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1, PINMUX4=B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2

Description

SYSCFG configuration register 3

Fields

PINMUX0

Pin GPIO multiplexer 0 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved

0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1): PB7
PINMUX1

Pin GPIO multiplexer 1 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved

0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4): PF2

1 (B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4): PA0

2 (B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4): PA1

3 (B_0x3_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4): PA2
PINMUX2

Pin GPIO multiplexer 2 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved Note: The PA11_RMP bit of the SYSCFG_CFGR1 takes priority over the selection through this bitfield. Refer to the description of the SYSCFG_CFGR1 register for more details.

0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5): PA8

1 (B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5): PA11
PINMUX3

Pin GPIO multiplexer 3 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved

0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8): PA14

1 (B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8): PB6

2 (B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8): PC15
PINMUX4

Pin GPIO multiplexer 4 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved Note: The PA12_RMP bit of the SYSCFG_CFGR1 takes priority over the selection through this bitfield. Refer to the description of the SYSCFG_CFGR1 register for more details.

0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2): PA7

1 (B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2): PA12
PINMUX5

Pin GPIO multiplexer 5 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.

0 (B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1): PA3

1 (B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1): PA4

2 (B_0x2_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1): PA5

3 (B_0x3_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1): PA6

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32