OC1FE=B_0x0, OC1CE=B_0x0, CC1S=B_0x0, CC2S=B_0x0, OC1PE=B_0x0, OC1M=B_0x0
| CC1S | Capture/Compare 1 selection 0 (B_0x0): CC1 channel is configured as output. 1 (B_0x1): CC1 channel is configured as input, IC1 is mapped on TI1. 2 (B_0x2): CC1 channel is configured as input, IC1 is mapped on TI2. 3 (B_0x3): CC1 channel is configured as input, IC1 is mapped on TRC. |
| OC1FE | Output compare 1 fast enable 0 (B_0x0): CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. 1 (B_0x1): An active edge on the trigger input acts like a compare match on CC1 output. |
| OC1PE | Output compare 1 preload enable 0 (B_0x0): Preload register on TIMx_CCR1 disabled. 1 (B_0x1): Preload register on TIMx_CCR1 enabled. |
| OC1M | OC1M[2:0]: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16. 0 (B_0x0): Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state. 1 (B_0x1): Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 2 (B_0x2): Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 3 (B_0x3): Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 4 (B_0x4): Force inactive level - OC1REF is forced low. 5 (B_0x5): Force active level - OC1REF is forced high. 6 (B_0x6): PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF= 0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1). 7 (B_0x7): PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. |
| OC1CE | Output compare 1 clear enable 0 (B_0x0): OC1Ref is not affected by the ETRF input 1 (B_0x1): OC1Ref is cleared as soon as a High level is detected on ETRF input |
| CC2S | Capture/Compare 2 selection 0 (B_0x0): CC2 channel is configured as output 1 (B_0x1): CC2 channel is configured as input, IC2 is mapped on TI2 2 (B_0x2): CC2 channel is configured as input, IC2 is mapped on TI1 3 (B_0x3): CC2 channel is configured as input, IC2 is mapped on TRC. |
| OC2FE | Output compare 2 fast enable |
| OC2PE | Output compare 2 preload enable |
| OC2M | OC2M[2:0]: Output compare 2 mode |
| OC2CE | Output compare 2 clear enable |
| OC1M_1 | OC1M[3] |
| OC2M_1 | OC2M[3] |