Regviz

stm32 /stm32f0 /STM32F0x0 /SYSCFG /CFGR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CFGR2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32f0/STM32F0x0/SYSCFG/CFGR2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LOCUP_LOCK)LOCUP_LOCK 0 (SRAM_PARITY_LOCK)SRAM_PARITY_LOCK 0 (PVD_LOCK)PVD_LOCK 0 (SRAM_PEF)SRAM_PEF

Description

configuration register 2

Fields

LOCUP_LOCK

Cortex-M0 LOCKUP bit enable bit
SRAM_PARITY_LOCK

SRAM parity lock bit
PVD_LOCK

PVD lock enable bit
SRAM_PEF

SRAM parity flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32