stm32 /stm32f0 /STM32F0x2 /CEC /CFGR

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Interpret as CFGR

31282724232019161512118743000000000000000000000000000000000000000000OAR0 (LSTN)LSTN0SFT0 (RXTOL)RXTOL0 (BRESTP)BRESTP0 (BREGEN)BREGEN0 (LBPEGEN)LBPEGEN

Description

configuration register

Fields

OAR

Own Address

LSTN

Listen mode

SFT

Signal Free Time

RXTOL

Rx-Tolerance

BRESTP

Rx-stop on bit rising error

BREGEN

Generate error-bit on bit rising error

LBPEGEN

Generate Error-Bit on Long Bit Period Error

Links

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