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stm32 /stm32f0 /STM32F0x2 /DBGMCU /APB1_FZ

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Interpret as APB1_FZ

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_TIM2_STOP)DBG_TIM2_STOP 0 (DBG_TIM3_STOP)DBG_TIM3_STOP 0 (DBG_TIM6_STOP)DBG_TIM6_STOP 0 (DBG_TIM7_STOP)DBG_TIM7_STOP 0 (DBG_TIM14_STOP)DBG_TIM14_STOP 0 (DBG_RTC_STOP)DBG_RTC_STOP 0 (DBG_WWDG_STOP)DBG_WWDG_STOP 0 (DBG_IWDG_STOP)DBG_IWDG_STOP 0 (DBG_I2C1_SMBUS_TIMEOUT)DBG_I2C1_SMBUS_TIMEOUT 0 (DBG_CAN_STOP)DBG_CAN_STOP

Description

Debug MCU APB1 freeze register

Fields

DBG_TIM2_STOP

TIM2 counter stopped when core is halted
DBG_TIM3_STOP

TIM3 counter stopped when core is halted
DBG_TIM6_STOP

TIM6 counter stopped when core is halted
DBG_TIM7_STOP

TIM7 counter stopped when core is halted
DBG_TIM14_STOP

TIM14 counter stopped when core is halted
DBG_RTC_STOP

Debug RTC stopped when core is halted
DBG_WWDG_STOP

Debug window watchdog stopped when core is halted
DBG_IWDG_STOP

Debug independent watchdog stopped when core is halted
DBG_I2C1_SMBUS_TIMEOUT

SMBUS timeout mode stopped when core is halted
DBG_CAN_STOP

CAN stopped when core is halted

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32