Regviz

stm32 /stm32f1 /STM32F100 /ADC1 /SMPR2

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Interpret as SMPR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SMP00SMP10SMP20SMP30SMP40SMP50SMP60SMP70SMP80SMP9

Description

sample time register 2

Fields

SMP0

Channel 0 sample time selection
SMP1

Channel 1 sample time selection
SMP2

Channel 2 sample time selection
SMP3

Channel 3 sample time selection
SMP4

Channel 4 sample time selection
SMP5

Channel 5 sample time selection
SMP6

Channel 6 sample time selection
SMP7

Channel 7 sample time selection
SMP8

Channel 8 sample time selection
SMP9

Channel 9 sample time selection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32