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stm32 /stm32f1 /STM32F100 /CEC /CFGR

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Interpret as CFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PE)PE 0 (IE)IE 0 (BTEM)BTEM 0 (BPEM)BPEM

Description

configuration register

Fields

PE

Peripheral enable
IE

Interrupt enable
BTEM

Bit timing error mode
BPEM

Bit period error mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32