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stm32 /stm32f1 /STM32F100 /CEC /CSR

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Interpret as CSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TSOM)TSOM 0 (TEOM)TEOM 0 (TERR)TERR 0 (TBTRF)TBTRF 0 (RSOM)RSOM 0 (REOM)REOM 0 (RERR)RERR 0 (RBTF)RBTF

Description

CEC control and status register

Fields

TSOM

Tx start of message
TEOM

Tx end of message
TERR

Tx error
TBTRF

Tx byte transfer request or block transfer finished
RSOM

Rx start of message
REOM

Rx end of message
RERR

Rx error
RBTF

Rx byte/block transfer finished

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32