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stm32 /stm32f1 /STM32F100 /DAC /DHR12LD

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Interpret as DHR12LD

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DACC1DHR0DACC2DHR

Description

DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved

Fields

DACC1DHR

DAC channel1 12-bit left-aligned data
DACC2DHR

DAC channel2 12-bit right-aligned data

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32