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stm32 /stm32f1 /STM32F100 /GPIOA /LCKR

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Interpret as LCKR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LCK0)LCK0 0 (LCK1)LCK1 0 (LCK2)LCK2 0 (LCK3)LCK3 0 (LCK4)LCK4 0 (LCK5)LCK5 0 (LCK6)LCK6 0 (LCK7)LCK7 0 (LCK8)LCK8 0 (LCK9)LCK9 0 (LCK10)LCK10 0 (LCK11)LCK11 0 (LCK12)LCK12 0 (LCK13)LCK13 0 (LCK14)LCK14 0 (LCK15)LCK15 0 (LCKK)LCKK

Description

Port configuration lock register

Fields

LCK0

Port A Lock bit 0
LCK1

Port A Lock bit 1
LCK2

Port A Lock bit 2
LCK3

Port A Lock bit 3
LCK4

Port A Lock bit 4
LCK5

Port A Lock bit 5
LCK6

Port A Lock bit 6
LCK7

Port A Lock bit 7
LCK8

Port A Lock bit 8
LCK9

Port A Lock bit 9
LCK10

Port A Lock bit 10
LCK11

Port A Lock bit 11
LCK12

Port A Lock bit 12
LCK13

Port A Lock bit 13
LCK14

Port A Lock bit 14
LCK15

Port A Lock bit 15
LCKK

Lock key

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32