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stm32 /stm32f1 /STM32F100 /SPI1 /CR2

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Interpret as CR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXDMAEN)RXDMAEN 0 (TXDMAEN)TXDMAEN 0 (SSOE)SSOE 0 (ERRIE)ERRIE 0 (RXNEIE)RXNEIE 0 (TXEIE)TXEIE

Description

control register 2

Fields

RXDMAEN

Rx buffer DMA enable
TXDMAEN

Tx buffer DMA enable
SSOE

SS output enable
ERRIE

Error interrupt enable
RXNEIE

RX buffer not empty interrupt enable
TXEIE

Tx buffer empty interrupt enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32