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stm32 /stm32f1 /STM32F107 /DBG /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_SLEEP)DBG_SLEEP 0 (DBG_STOP)DBG_STOP 0 (DBG_STANDBY)DBG_STANDBY 0 (TRACE_IOEN)TRACE_IOEN 0TRACE_MODE 0 (DBG_IWDG_STOP)DBG_IWDG_STOP 0 (DBG_WWDG_STOP)DBG_WWDG_STOP 0 (DBG_TIM1_STOP)DBG_TIM1_STOP 0 (DBG_TIM2_STOP)DBG_TIM2_STOP 0 (DBG_TIM3_STOP)DBG_TIM3_STOP 0 (DBG_TIM4_STOP)DBG_TIM4_STOP 0 (DBG_CAN1_STOP)DBG_CAN1_STOP 0 (DBG_I2C1_SMBUS_TIMEOUT)DBG_I2C1_SMBUS_TIMEOUT 0 (DBG_I2C2_SMBUS_TIMEOUT)DBG_I2C2_SMBUS_TIMEOUT 0 (DBG_TIM5_STOP)DBG_TIM5_STOP 0 (DBG_TIM6_STOP)DBG_TIM6_STOP 0 (DBG_TIM7_STOP)DBG_TIM7_STOP 0 (DBG_CAN2_STOP)DBG_CAN2_STOP

Description

DBGMCU_CR

Fields

DBG_SLEEP

DBG_SLEEP
DBG_STOP

DBG_STOP
DBG_STANDBY

DBG_STANDBY
TRACE_IOEN

TRACE_IOEN
TRACE_MODE

TRACE_MODE
DBG_IWDG_STOP

DBG_IWDG_STOP
DBG_WWDG_STOP

DBG_WWDG_STOP
DBG_TIM1_STOP

DBG_TIM1_STOP
DBG_TIM2_STOP

DBG_TIM2_STOP
DBG_TIM3_STOP

DBG_TIM3_STOP
DBG_TIM4_STOP

DBG_TIM4_STOP
DBG_CAN1_STOP

DBG_CAN1_STOP
DBG_I2C1_SMBUS_TIMEOUT

DBG_I2C1_SMBUS_TIMEOUT
DBG_I2C2_SMBUS_TIMEOUT

DBG_I2C2_SMBUS_TIMEOUT
DBG_TIM5_STOP

DBG_TIM5_STOP
DBG_TIM6_STOP

DBG_TIM6_STOP
DBG_TIM7_STOP

DBG_TIM7_STOP
DBG_CAN2_STOP

DBG_CAN2_STOP

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32