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stm32 /stm32f1 /STM32F107 /RCC /CFGR2

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Interpret as CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PREDIV10PREDIV20PLL2MUL0PLL3MUL0 (PREDIV1SRC)PREDIV1SRC 0 (I2S2SRC)I2S2SRC 0 (I2S3SRC)I2S3SRC

Description

Clock configuration register2 (RCC_CFGR2)

Fields

PREDIV1

PREDIV1 division factor
PREDIV2

PREDIV2 division factor
PLL2MUL

PLL2 Multiplication Factor
PLL3MUL

PLL3 Multiplication Factor
PREDIV1SRC

PREDIV1 entry clock source
I2S2SRC

I2S2 clock source
I2S3SRC

I2S3 clock source

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32