Regviz

stm32 /stm32f3 /STM32F301 /ADC /TR1

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Interpret as TR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LT10HT1

Description

ADC watchdog threshold register 1

Fields

LT1

Analog watchdog 1 lower threshold
HT1

Analog watchdog 1 higher threshold

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32