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stm32 /stm32f3 /STM32F301 /RCC /APB1RSTR

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Interpret as APB1RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM2RST)TIM2RST 0 (TIM6RST)TIM6RST 0 (WWDGRST)WWDGRST 0 (SPI2RST)SPI2RST 0 (SPI3RST)SPI3RST 0 (USART2RST)USART2RST 0 (USART3RST)USART3RST 0 (I2C1RST)I2C1RST 0 (I2C2RST)I2C2RST 0 (PWRRST)PWRRST 0 (DACRST)DACRST 0 (CECRST)CECRST

Description

APB1 peripheral reset register (RCC_APB1RSTR)

Fields

TIM2RST

Timer 2 reset
TIM6RST

Timer 6 reset
WWDGRST

Window watchdog reset
SPI2RST

SPI2 reset
SPI3RST

SPI3 reset
USART2RST

USART 2 reset
USART3RST

USART3 reset
I2C1RST

I2C1 reset
I2C2RST

I2C2 reset
PWRRST

Power interface reset
DACRST

DAC interface reset
CECRST

HDMI CEC reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32