Regviz

stm32 /stm32f3 /STM32F301 /RCC /APB2ENR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as APB2ENR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32f3/STM32F301/RCC/APB2ENR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYSCFGEN)SYSCFGEN 0 (TIM1EN)TIM1EN 0 (USART1EN)USART1EN 0 (TIM15EN)TIM15EN 0 (TIM16EN)TIM16EN 0 (TIM17EN)TIM17EN

Description

APB2 peripheral clock enable register (RCC_APB2ENR)

Fields

SYSCFGEN

SYSCFG clock enable
TIM1EN

TIM1 Timer clock enable
USART1EN

USART1 clock enable
TIM15EN

TIM15 timer clock enable
TIM16EN

TIM16 timer clock enable
TIM17EN

TIM17 timer clock enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32