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stm32 /stm32f3 /STM32F301 /RCC /CFGR2

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Interpret as CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PREDIV0ADC1PRES

Description

Clock configuration register 2

Fields

PREDIV

PREDIV division factor
ADC1PRES

ADC1 prescaler

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32