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stm32 /stm32f3 /STM32F301 /TIM1 /OR

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Interpret as OR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IM1_ETR_ADC1_RMP

Description

Option registers

Fields

IM1_ETR_ADC1_RMP

TIM1_ETR_ADC1 remapping capability

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32