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stm32 /stm32f3 /STM32F373 /SDADC1 /CR1

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Interpret as CR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EOCALIE)EOCALIE 0 (JEOCIE)JEOCIE 0 (JOVRIE)JOVRIE 0 (REOCIE)REOCIE 0 (ROVRIE)ROVRIE 0REFV 0 (SLOWCK)SLOWCK 0 (SBI)SBI 0 (PDI)PDI 0 (JSYNC)JSYNC 0 (RSYNC)RSYNC 0 (JDMAEN)JDMAEN 0 (RDMAEN)RDMAEN 0 (INIT)INIT

Description

control register 1

Fields

EOCALIE

End of calibration interrupt enable
JEOCIE

Injected end of conversion interrupt enable
JOVRIE

Injected data overrun interrupt enable
REOCIE

Regular end of conversion interrupt enable
ROVRIE

Regular data overrun interrupt enable
REFV

Reference voltage selection
SLOWCK

Slow clock mode enable
SBI

Enter Standby mode when idle
PDI

Enter power down mode when idle
JSYNC

Launch a injected conversion synchronously with SDADC1
RSYNC

Launch regular conversion synchronously with SDADC1
JDMAEN

DMA channel enabled to read data for the injected channel group
RDMAEN

DMA channel enabled to read data for the regular channel
INIT

Initialization mode request

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32