Regviz

stm32 /stm32f3 /STM32F373 /TIM2 /OR

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Interpret as OR

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https://regviz.com/r/stm32/stm32f3/STM32F373/TIM2/OR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ITR1_RMP

Description

option register

Fields

ITR1_RMP

Internal trigger 1 remap

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32