Regviz

stm32 /stm32f4 /STM32F412 /I2C3 /OAR1

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Interpret as OAR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADD0)ADD0 0ADD70ADD10 0 (ADDMODE)ADDMODE

Description

Own address register 1

Fields

ADD0

Interface address
ADD7

Interface address
ADD10

Interface address
ADDMODE

Addressing mode (slave mode)

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32