PWRFF=B_0x0, CMDFF=B_0x0, CMDFE=B_0x0, PWRFE=B_0x0, RCB=B_0x0, PRDFF=B_0x0, PRDFE=B_0x0
DSI Host generic packet status register
| CMDFE | Command FIFO empty This bit indicates the empty status of the generic command FIFO: 0 (B_0x0): Write payload FIFO not empty 1 (B_0x1): Write payload FIFO empty |
| CMDFF | Command FIFO full This bit indicates the full status of the generic command FIFO: 0 (B_0x0): Write payload FIFO not full 1 (B_0x1): Write payload FIFO full |
| PWRFE | Payload write FIFO empty This bit indicates the empty status of the generic write payload FIFO: 0 (B_0x0): Write payload FIFO not empty 1 (B_0x1): Write payload FIFO empty |
| PWRFF | Payload write FIFO full This bit indicates the full status of the generic write payload FIFO: 0 (B_0x0): Write payload FIFO not full 1 (B_0x1): Write payload FIFO full |
| PRDFE | Payload read FIFO empty This bit indicates the empty status of the generic read payload FIFO: 0 (B_0x0): Read payload FIFO not empty 1 (B_0x1): Read payload FIFO empty |
| PRDFF | Payload read FIFO full This bit indicates the full status of the generic read payload FIFO: 0 (B_0x0): Read payload FIFO not full 1 (B_0x1): Read payload FIFO ful. |
| RCB | Read command busy This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO: 0 (B_0x0): No read command on going 1 (B_0x1): Read command on going |