DSI Host PHY status register
| PD | PHY direction This bit indicates the status of phydirection D-PHY signal. |
| PSSC | PHY stop state clock lane This bit indicates the status of phystopstateclklane D-PHY signal. |
| UANC | ULPS active not clock lane This bit indicates the status of ulpsactivenotclklane D-PHY signal. |
| PSS0 | PHY stop state lane 0 This bit indicates the status of phystopstate0lane D-PHY signal. |
| UAN0 | ULPS active not lane 1 This bit indicates the status of ulpsactivenot0lane D-PHY signal. |
| RUE0 | RX ULPS escape lane 0 This bit indicates the status of rxulpsesc0lane D-PHY signal. |
| PSS1 | PHY stop state lane 1 This bit indicates the status of phystopstate1lane D-PHY signal. |
| UAN1 | ULPS active not lane 1 This bit indicates the status of ulpsactivenot1lane D-PHY signal. |