HSIDL0=B_0x0, THSPREPEN=B_0x0, THSTRAILEN=B_0x0, TCLKPOSTEN=B_0x0, PDEN=B_0x0, SWDL1=B_0x0, SWDL0=B_0x0, TCLKZEROEN=B_0x0, TLPXDEN=B_0x0, TCLKPREPEN=B_0x0, TLPXCEN=B_0x0, HSICL=B_0x0, HSIDL1=B_0x0, TDDL=B_0x0, SWCL=B_0x0, FTXSMDL=B_0x0, CDOFFDL=B_0x0, THSEXITEN=B_0x0, FTXSMCL=B_0x0, THSZEROEN=B_0x0
DSI Wrapper PHY configuration register 0
| UIX4 | Unit interval multiplied by 4 This field defines the bit period in high-speed mode in unit of 0.25 ns. As an example, if the unit interval is 3 ns, a value of twelve (0x0C) must be driven to this input. This value is used to generate delays. If the period is not a multiple of 0.25 ns, the value driven must be rounded down. For example, a 600 Mbit/s link uses a unit interval of 1.667 ns, which, multiplied by four gives 6.667 ns. In this case a value of 6 (not 7) must be driven onto the ui_x4 input. |
| SWCL | Swap clock lane pins This bit swaps the pins on clock lane. 0 (B_0x0): Regular clock lane pin configuration 1 (B_0x1): Swapped clock lane pin |
| SWDL0 | Swap data lane 0 pins This bit swaps the pins on data lane 0. 0 (B_0x0): Regular clock lane pin configuration 1 (B_0x1): Swapped clock lane pin |
| SWDL1 | Swap data lane 1 pins This bit swaps the pins on clock lane. 0 (B_0x0): Regular clock lane pin configuration 1 (B_0x1): Swapped clock lane pin |
| HSICL | Invert high-speed data signal on clock lane This bit inverts the high-speed data signal on clock lane. 0 (B_0x0): Normal data configuration 1 (B_0x1): Inverted data configuration |
| HSIDL0 | Invert the high-speed data signal on data lane 0 This bit inverts the high-speed data signal on clock lane. 0 (B_0x0): Normal data signal configuration 1 (B_0x1): Inverted data signal configuration |
| HSIDL1 | Invert the high-speed data signal on data lane 1 This bit inverts the high-speed data signal on data lane 1. 0 (B_0x0): Normal data signal configuration 1 (B_0x1): Inverted data signal configuration |
| FTXSMCL | Force in TX Stop mode the clock lane This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. 0 (B_0x0): No effect 1 (B_0x1): Force the clock lane in TX Stop mode |
| FTXSMDL | Force in TX Stop mode the data lanes This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. 0 (B_0x0): No effect 1 (B_0x1): Force the data lanes in TX Stop mode |
| CDOFFDL | Contention detection OFF on data lanes When only forward escape mode is used, this signal can be made high to switch off the contention detector and reduce static power consumption. 0 (B_0x0): Contention detection on data lane ON 1 (B_0x1): Contention detection on data lane OFF |
| TDDL | Turn disable data lanes This bit forces the data lane to remain in RX event if it receives a bus-turn-around request from the other side. 0 (B_0x0): No effect 1 (B_0x1): Force data lanes in RX mode after a BTA |
| PDEN | Pull-down enable This bit enables a pull-down on the lane to prevent from floating states when unused. 0 (B_0x0): Pull-down on lanes disabled 1 (B_0x1): Pull-down on lanes enabled |
| TCLKPREPEN | Custom time for tCLK-PREPARE enable This bit enables the manual programming of tCLK-PREPARE duration in the D-PHY. The desired value must be programmed in the TLKCPREP field of the DSI_WPCR2 register. 0 (B_0x0): Default value is used for tCLK-PREPARE 1 (B_0x1): Programmable value is used for tCLK-PREPARE |
| TCLKZEROEN | Custom time for tCLK-ZERO enable This bit enables the manual programming of tCLK-ZERO duration in the D-PHY. The desired value must be programmed in the TCLKZERO field of the DSI_WPCR2 register. 0 (B_0x0): Default value is used for tCLK-ZERO. 1 (B_0x1): Programmable value is used for tCLK-ZERO. |
| THSPREPEN | Custom time for tHS-PREPARE enable This bit enables the manual programming of tHS-PREPARE duration in the D-PHY. The desired value must be programmed in the THSPREP field of the DSI_WPCR2 register. 0 (B_0x0): Default value is used for tHS-PREPARE. 1 (B_0x1): Programmable value is used for tHS-PREPARE. |
| THSTRAILEN | Custom time for tHS-TRAIL enable This bit enables the manual programming of THS-TRAIL duration in the D-PHY. The desired value must be programmed in the THSRAIL field of the DSI_WPCR2 register. 0 (B_0x0): Default value is used for THS-TRAIL. 1 (B_0x1): Programmable value is used for THS-TRAIL. |
| THSZEROEN | Custom time for tHS-ZERO enable This bit enables the manual programming of tHS-ZERO duration in the D-PHY. The desired value must be programmed in the THSZERO field of the DSI_WPCR3 register. 0 (B_0x0): Default value is used for tHS-ZERO. 1 (B_0x1): Programmable value is used for tHS-ZERO. |
| TLPXDEN | Custom time for tLPX for data lanes enable This bit enables the manual programming of TLPX duration for the data lanes in the D-PHY. The desired value must be programmed in the TLPXD field of the DSI_WPCR3 register. 0 (B_0x0): Default value is used for TLPX for the data lanes. 1 (B_0x1): Programmable value is used for TLPX for the data lanes. |
| THSEXITEN | Custom time for tHS-EXIT enable This bit enables the manual programming of tHS-EXIT duration in the D-PHY. The desired value must be programmed in the THSEXIT field of the DSI_WPCR3 register. 0 (B_0x0): Default value is used for tHS-EXIT. 1 (B_0x1): Programmable value is used for tHS-EXIT. |
| TLPXCEN | Custom time for tLPX for clock lane enable This bit enables the manual programming of tLPX duration for the clock lane in the D-PHY. The desired value must be programmed in the TLPXC field of the DSI_WPCR3 register. 0 (B_0x0): Default value is used for tLPX for the clock lane. 1 (B_0x1): Programmable value is used for tLPX for the clock lane. |
| TCLKPOSTEN | Custom time for tCLK-POST enable This bit enables the manual programming of tCLK-POST duration in the D-PHY. The desired value must be programmed in the TCLKPOST field of the DSI_WPCR4 register. 0 (B_0x0): Default value is used for tCLKPOST. 1 (B_0x1): Programmable value is used for tCLKPOST. |