FLPRXLPM=B_0x0, SDDC=B_0x0
DSI Wrapper PHY configuration register 1
| HSTXDCL | High-speed transmission delay on clock lane Delay tuner control to change delay (up to DP/DN) in clock path. Can be used to change clock edge position with respect to data bit transitions on DP/DN. Default value = 00. |
| HSTXDDL | High-speed transmission delay on data lanes Delay tuner control to change delay (up to DP/DN) in data path. Can be used to change data edge transition positions with respect to clock edge on DP/DN. Default value = 00. |
| LPSRCCL | Low-power transmission slew-rate compensation on clock lane Can be used to change slew-rate of clock lane LP transitions. Default value = 00. |
| LPSRCDL | Low-power transmission slew-rate compensation on data lanes Can be used to change slew-rate of data lane LP transitions. Default value = 00. |
| SDDC | SDD control This bit switches on the additional current path to meet the SDDTx parameter defined by MIPI D-PHY Specification on both clock and data lanes. 0 (B_0x0): No effect 1 (B_0x1): Activate additional current path on all lanes |
| HSTXSRCCL | High-speed transmission slew-rate control on clock lane Slew-rate control for high-speed transmitter output. It can be used to change slew-rate of clock lane HS transitions. Default value = 00. |
| HSTXSRCDL | High-speed transmission slew-rate control on data lanes Slew-rate control for high-speed transmitter output. It can be used to change slew-rate of data lane HS transitions. Default value = 00. |
| FLPRXLPM | Forces LP receiver in low-power mode This bit enables the low-power mode of LP receiver (LPRX). When set, the LPRX operates in low-power mode all the time (when this is not activated, LPRX operates in low power mode during ULPS only). 0 (B_0x0): No effect 1 (B_0x1): LPRX is forced in low-power mode. |
| LPRXFT | Low-power RX low-pass filtering tuning This signal can be used to tune the cutoff frequency of low-pass filter at the input of LPRX. |