IDF=B_0x0, ODF=B_0x0, PLLEN=B_0x0, REGEN=B_0x0
DSI Wrapper regulator and PLL control register
| PLLEN | PLL enable This bit enables the D-PHY PLL. 0 (B_0x0): PLL disabled 1 (B_0x1): PLL enabled |
| NDIV | PLL loop division factor This field configures the PLL loop division factor. 10 to 125: Allowed loop division factor values Others: Reserved |
| IDF | PLL input division factor This field configures the PLL input division factor. 0 (B_0x0): PLL input divided by 1 1 (B_0x1): PLL input divided by 1 2 (B_0x2): PLL input divided by 2 3 (B_0x3): PLL input divided by 3 4 (B_0x4): PLL input divided by 4 5 (B_0x5): PLL input divided by 5 6 (B_0x6): PLL input divided by 6 7 (B_0x7): PLL input divided by 7 |
| ODF | PLL output division factor This field configures the PLL output division factor. 0 (B_0x0): PLL output divided by 1 1 (B_0x1): PLL output divided by 2 2 (B_0x2): PLL output divided by 4 3 (B_0x3): PLL output divided by 8 |
| REGEN | Regulator enable This bit enables the DPHY regulator. 0 (B_0x0): regulator disabled 1 (B_0x1): regulator enabled |